Structure and method for thin single or multichip semiconductor QFN packages

ABSTRACT

A semiconductor device ( 100 ) has one or more semiconductor chips ( 110 ) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments ( 111 ) separated from the chip by gaps ( 120 ); the segments have first and second surfaces, wherein the second surfaces ( 111   b ) are coplanar ( 130 ) with the passive chip surface ( 101   b ). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound ( 150 ) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar ( 130 ) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces.

FIELD OF THE INVENTION

The present invention is related in general to the field ofsemiconductor devices and processes, and more specifically to structureand method of thin single or multichip semiconductor QFN devices.

DESCRIPTION OF THE RELATED ART

Leadframes for semiconductor devices provide a stable support pad forfirmly positioning the semiconductor chip, usually an integrated circuit(IC) chip, within a package. It has been common practice to manufacturesingle piece leadframes from thin (about 120 to 250 μm) sheets of metal.For electrical and thermal reasons, copper has been the favoritestarting material; however, the copper price has recently been climbingsharply.

In addition to the chip pad, the leadframe offers a plurality ofconductive segments to bring various electrical conductors into closeproximity of the chip. The remaining gaps between the segments and thecontact pads on the chip surface are bridged by connectors, typicallythin metal wires of gold, individually bonded to the chip contact padsand the leadframe segments. Consequently, the surface of the innersegment ends has to be metallurgically suitable for attaching theconnectors.

The end of the lead segments remote from the chip need to beelectrically and mechanically connected to external circuitry such asprinted circuit boards. This attachment is customarily performed bysoldering, conventionally with a tin alloy solder at a reflowtemperature above 200° C. Consequently, the surface of the outer segmentends needs to have a metallurgical configuration suitable for reflowattachment to external parts.

Finally, the leadframe provides the framework for encapsulating thesensitive chip and fragile connecting wires. Encapsulation using plasticmaterials has been the preferred method due to low cost. The transfermolding process for epoxy-based thermoset compounds at 175° C. has beenpracticed for many years. The temperature of 175° C. for molding andmold curing (polymerization) is compatible with the temperature of >200°C. for eutectic solder reflow.

Reliability tests in moist environments require that the moldingcompounds have good adhesion to the leadframe and the device parts itencapsulates. Two major contributors to good adhesion are the chemicalaffinity between the molding compound and the metal finish of theleadframe, and the surface roughness of the leadframe.

In recent years, a number of technical and market trends have made itmore and more difficult to find satisfactory solutions for the diverserequirements. As an example, the package dimensions are shrinking,offering less surface for adhesion. Then, the requirement to uselead-free solders pushes the reflow temperature range into theneighborhood of about 260° C., making it more difficult to maintain moldcompound adhesion to the leadframes. This is especially true for thesmall leadframe surfaces available in QFN (Quad Flat No-lead) and SON(Small Outline No-lead) devices. ICs are becoming faster; consequently,they dissipate more thermal energy, which needs to be removed tomaintain optimum operating temperatures. The dimensions of semiconductorpackages, especially the thickness, have to shrink since they need tofit into small, often handheld end-equipment. And the packagemanufacturing cost must come down to compensate for rising materialprices and market pressures on the product cost.

SUMMARY OF THE INVENTION

Applicant recognizes the need for a fresh concept of achieving low-costdevice fabrication using leadframe structures tailor-made for thinsemiconductor packages and high reliability devices. The low-costleadframes are to offer a combination of adhesion to molding compounds,bondability for connecting wires, solderablity of the exposed leadframesegments, and short paths for thermal power dissipation.

There are technical advantages, when the leadframe and its method offabrication are flexible and low cost enough to be applied for differentsemiconductor product families and a wide spectrum of design andassembly variations, and achieve improvements toward the goals ofimproved process yields, high manufacturing throughput, and devicereliability. Of special interest are solutions, which can be applied tosingle and multi-chip products. There are further technical advantages,when these innovations are accomplished using the installed equipmentbase so that no investment in new manufacturing machines is needed.

One embodiment of the invention is a semiconductor device, which has oneor more semiconductor chips with active and passive surfaces, whereinthe active surfaces include contact pads. The device further has aplurality of metal segments separated from the chip by gaps; thesegments have first and second surfaces, wherein the second surfaces areflat and coplanar with the passive chip surface. Conductive connectorsspan from the chip contact pads to the respective first segment surface.Polymeric encapsulation compound covers the active chip surface, theconnectors, and the first segment surfaces, and are filling the gaps sothat the compound forms surfaces coplanar with the passive chip surfaceand the second segment surfaces. In this structure, the device thicknessmay be only about 250 μm. Reflow metals may be on the passive chipsurface and the second segment surfaces.

Another embodiment of the invention is a method for fabricatingsemiconductor devices. Using a metal sheet with first and secondsurfaces, selected portions of the first sheet surface are etched sothat they become gaps with a certain depth and selected lengths andwidths between un-etched metal segments. Semiconductor chips withcontact pads are attached in gaps of suitable length and width. The chipcontact pads are connected to respective segments using conductiveconnectors. The first sheet surface including the assembled chips andconnectors are covered with a polymeric compound, which also fills theremaining gaps. Mechanical grinding is then applied to the second sheetsurface in order to remove metal until the certain depth of the gaps isreached. The segments are thus electrically isolated from each other,and a planar device surface is created. The grinding process may becontinued until a predetermined thinness of segments and chips isreached, for some devices as low as about 250 μm.

Another embodiment of the invention is another method for fabricatingsemiconductor devices. Using a metal sheet with first and secondsurfaces, selected portions of the first sheet surface are etched sothat they become gaps with a certain depth and selected lengths andwidths between un-etched metal segments; the segments are suitable forattaching semiconductor chips or metal connectors. Chips with contactpads are attached to suitable segments, and chip contact pads areconnected to respective segments using conductive connectors. The firstsheet surface including the assembled chips and connectors are coveredwith a polymeric compound, which also fills the gaps. Mechanicalgrinding is then applied to the second sheet surface in order to removemetal until the certain depth of the gaps is reached. The segments arethus electrically isolated from each other, and a planar device surfaceis created. The grinding process may be continued until a predeterminedthinness of the segments is reached, for some devices as low as about375 μm.

It is an advantage that the grinding technique does not require specificpowders, rinsing or cleaning, and the grinding rate is equal for theinvolved metals, polymers, and semiconductors. The employed technique iseasy to control, an advantage for fabricating ultra-thin packages.

The technical advances represented by certain embodiments of theinvention will become apparent from the following description of thepreferred embodiments of the invention, when considered in conjunctionwith the accompanying drawings and the novel features set forth in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic cross section of a device of the multichipQFN/SON type having a structure fabricated by a method according to theinvention.

FIG. 2 shows a schematic cross section of another device of themultichip QFN/SON type having a structure fabricated by a methodaccording to the invention.

FIGS. 3 to 5B are schematic cross sections to illustrate method stepsfor an embodiment of the invention.

FIG. 3 depicts a metal sheet after partial etching.

FIG. 4 illustrates semiconductor chips after assembling on the partiallyetched metal sheet, and after encapsulating.

FIG. 5A shows the device after the first phase of mechanical grinding.

FIG. 5B shows the device after the second phase of mechanical grinding.

FIGS. 6 to 8B are schematic cross sections to illustrate method stepsfor another embodiment of to the invention.

FIG. 6 depicts a metal sheet after partial etching.

FIG. 7 illustrates semiconductor chips after assembling on the partiallyetched metal sheet, and after encapsulating.

FIG. 8A shows the device after the first phase of mechanical grinding.

FIG. 8B shows the device after the second phase of mechanical grinding.

FIG. 9 is a cross section showing schematically the grinding system usedby the method of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1 and 2 are schematic cross sections of embodiments of the presentinvention. FIG. 1 shows a multichip device of the QFN (Quad FlatNo-lead) or SON (Small Outline No-lead) family, generally designated100, with two similar chips 101 and 102. It should be stressed, however,that the considerations about device 100 are equally valid, when device100 contains only a single chip, or more than two chips; also, theconsiderations are equally valid, when the chips of a multichip deviceare dissimilar or belonging to different product families.

Using chip 101 as an example, FIG. 1 illustrates chip 101 having anactive surface 101 a and a passive surface 101 b. The active surface 101a includes contact pads suitable for affixing conductive connectors. Inanalogy, chip 102 has an active surface 102 a with contact pads, and apassive surface 102 b.

Device 100 in FIG. 1 further has a plurality of metal segments 110, 111,etc., which are separated from chips 101 and 102 by gaps, and by othergaps from each other. For instance, segment 110 is separated from chip101 by gap 120. The segments have first and second surfaces; forexample, segment 110 has first surface 110 a and second surface 110 b;and segment 111 has first surface 111 a and second surface 111 b. Thesecond surfaces 110 b, 111 b, etc., are coplanar with the passive chipsurface 101 b, and furthermore with passive chip surface 102 b and thesecond surfaces of all other segments. With other words, all chippassive surfaces and all segment second surfaces are in the same plane130.

Conductive connectors are spanning from the chip contact pads to thefirst surface of the respective segment. In FIG. 1, the connectors arebond wires; for instance, one contact pad of chip 101 is shown connectedto segment 110 by wire 140, and the other contact pad connected by wire141 to segment 111.

Polymeric encapsulation compound 150, preferably an epoxy-based moldingcompound, covers the active chip surfaces 101 a and 102 a, theconnectors 140, 141, etc., and the first segment surfaces 110 a, 111 a,etc. In addition, encapsulation compound 150 fills the gaps 120 etc. sothat the compound forms surfaces 150 a, 150 b . . . 150 n coplanar withthe passive chip surfaces 101 b and 102 b and the second segmentsurfaces 110 b, 111 b, etc. With other words, all chip passive surfaces,all segment second surfaces and the surfaces of the gap-filling compoundare in the same pane 130.

Devices as depicted in FIG. 1 can be fabricated with very slim thickness160. As an example, with segment thickness 160 a of 75 μm, wire spanloop height 160 b of 75 μm, and encapsulation compound thickness 160 cover the wire span of 100 μm, the total device thickness 160 is only 250μm. In this example, the thickness of the semiconductor chips may be 100μm or even only 75 μm.

For many applications, it is preferred to provide the connection toexternal parts using solder reflow alloys. To this end, reflow material(for example, solder balls or solder paste) is attached to the secondsegments surfaces 110 b, 111 b, etc., and preferably also to the passivechip surfaces 101 b and 102 b. For other applications, the connection toexternal parts is accomplished by pressure contacts.

For some applications, it is advantageous to include at least onepassive component inside of the encapsulation compound.

Another embodiment of the invention is illustrated in FIG. 2 as amultichip device of the QFN or SON type, generally designated 200. Theembodiment is shown with two chips 201 and 202, which may be similar ordifferent. It should be stressed, however, that the considerations aboutdevice 200 are equally valid, when device 200 contains only a singlechip, or more than two chips. The active surfaces of chips 201 and 202have contact pads.

Device 200 has a plurality of metal segments 210, 211, 212, etc., whichare separated from each other by gaps. For instance, segment 210 isseparated from segment 211 by gap 220. The segments have first andsecond surfaces; for example, segment 210 has first surface 210 a andsecond surface 210 b; and segment 211 has first surface 211 a and secondsurface 211 b. The second surfaces 210 b, 211 b, etc., are coplanar; allsegment second surfaces are in the same plane 230.

The first segment surfaces are suitable for attaching semiconductorchips or conductive connectors. In the example of FIG. 2, the firstsurface 210 a of segment 210 is suitable for attaching a bond wire; thefirst surface 211 a of segment 211 has an area suitable for attachingthe passive surface of semiconductor chip 201.

Conductive connectors are spanning from the chip contact pads to thefirst surface of the respective segment. In FIG. 2, the connectors arebond wires; for instance, one contact pad of chip 201 is shown connectedto segment 210 by wire 240, and the other contact pad connected by wire241 to segment 212.

Polymeric encapsulation compound 250, preferably an epoxy-based moldingcompound, covers the active chip surfaces, the connectors 240, 241,etc., and the first segment surfaces 210 a, 211 a, etc. In addition,encapsulation compound 250 fills the gaps 220 etc. so that the compoundforms surfaces 250 a, 250 b . . . 250 n coplanar with the second segmentsurfaces 210 b, 211 b, etc. All segment second surfaces and the surfacesof the gap-filling compound are in the same pane 230.

Devices as depicted in FIG. 2 can be fabricated with slim thickness 260.As an example, with segment thickness 260 a of 100 μm, chip thickness260 b of 100 μm, wire span loop height 260 c of 75 μm, and encapsulationcompound thickness 260 d over the wire span of 100 μm, the total devicethickness 260 is only 375 μm.

For many applications, it is preferred to provide the connection toexternal parts using solder reflow alloys. To this end, reflow material(for example, solder balls or solder paste) is attached to the secondsegments surfaces 210 b, 211 b, etc. For other applications, theconnection to external parts is accomplished by pressure contacts.

For some applications, it is advantageous to include at least onepassive component inside of the encapsulation compound.

Other embodiments of the present invention are methods for fabricatingsemiconductor devices. Specifically, FIGS. 3 to 5B illustrate steps ofthe fabrication process for devices of the structure displayed in FIG.1,and FIGS. 6 to 8B depict steps of the fabrication process for devices ofthe structure displayed in FIG. 2. In both fabrication methods, a metalsheet is provided, which has first and second surfaces. Preferred sheetmetals are copper or copper alloys; alternative metals include aluminum,iron-nickel alloys, and Kovar. The preferred metal sheet thickness is inthe range from 100 to 300 μm; thinner sheets are possible, but notnecessary, since the sheets will be thinned at end of the process bygrinding (see below). The ductility in this thickness range provides the5 to 15% elongation that facilitates the segment bending and formingoperation needed for some of the finished devices (for instance, forsurface mount devices).

Referring now to FIG. 3, selected portions of the first surface 301 a ofsheet 301 are etched so that the etched portions become gaps with acertain depth 302 a and selected length 302 b and width (not shown inthe cross section of FIG. 3) between un-etched metal segments 303. Thedepth, length and width of the gaps are predetermined to accommodatesemiconductor chips, and the segments are predetermined (metallurgicallysuitable) for attaching metal connectors on first surface 301 a. Thesheet portion left after the etch step acts as sort of “carrier” andincludes the second surface 301 b of the sheet.

In the next process step, semiconductor chips with contact pads areprovided; the number of required chips is determined by the finalproduct (single chip or multi-chip device). Each chip is placed in a gapof suitable length and width, and attached to the etched metal sheet.FIG. 4 illustrates examples for chips 401, which fit easily in thelength 302 b of the etched gaps. The thickness of chips 401 may be equalto, or smaller or larger than depth 302 a.

FIG. 4 also shows the next process step of interconnecting the chipcontact pads with the respective segments 303 using conductiveconnectors 402. Preferred connectors are bond wires made of gold or goldalloy. In addition, FIG. 4 depicts the next process step of covering thefirst sheet surface 301 a, the assembled chips 401, and the connectors402 with a polymeric compound 403, preferably an epoxy-based moldingcompound; actually, compound 403 covers the connectors 402 to a height410 over the wire span to ensure complete protection. For many devices,the top surface 403 a of the encapsulation compound is preferablysubstantially planar and parallel to the second sheet surface 301 b.Furthermore, compound 403 is filling the remaining gaps. On the otherhand, second sheet surface 301 b remains uncovered by the encapsulationcompound.

FIGS. 5A and 5B illustrate the mechanical grinding step at twocompletion stages, FIG. 5A at an earlier completion stage and FIG. 5B ata later completion stage. For the grinding process (described in moredetail in conjunction with FIG. 9), a rotating grinding wheel 501 isused similar to the wheel conventionally used in the silicon waferback-grinding process. The grinding process attacks the second sheetsurface 301 b (see FIG. 4) and continues to remove metal, until thesheet metal (the “carrier”) leftover from the etching step of FIG. 3 isremoved and the certain depth 302 a of the gaps etched in FIG. 3 isreached. At this stage of the grinding step, the segments 303 becomeelectrically isolated from each other and the passive surface of chips401 becomes exposed. The grinding step creates a common planar devicesurface, where the passive surface of chips 401, the segments 303, andthe compound-filled gaps are aligned in a common plane 530.

This stage of the grinding process is captured in FIG. 5A. It leaves thethickness 560 of the finished device at a value, which satisfies thespecifications of many products. However, for other devices the grindingprocess may continue, see FIG. 5B, until a thinner predeterminedthickness of the segments, the chips, and thus the overall device 561 isreached.

The device fabrication process may further include the step of attachingreflow metals, such as tin-based solders, to the segments and chipsexposed at the planar device surface 530 to prepare for solderattachment of the device to external parts.

Referring now to the alternative process flow, FIG. 6 displays the metalsheet, after selected portions of the first sheet surface 601 a havebeen etched so that the etched portions become gaps with a certain depth602 a and selected length 602 b and width (not shown in the crosssection of FIG. 6) between un-etched metal segments 603 and 604. Thesegments 603 are predetermined (metallurgically suitable) for attachingmetal connectors on first surface 601 a, and the segments 604 arepredetermined (metallurgically suitable) for attaching semiconductorchips. The sheet portion left after the etch step acts as sort of“carrier” and includes the second surface 601 b of the sheet.

In the next process step, semiconductor chips with contact pads areprovided; the number of required chips is determined by the finalproduct (single chip or multi-chip device). Each chip is placed on asegment 604 of suitable length and width, and attached to the segment.FIG. 7 illustrates examples for chips 701 on segments 604. The thicknessof chips 701 may be selected as required by the device type.

FIG. 7 also shows the next process step of interconnecting the chipcontact pads with the respective segments 603 using conductiveconnectors 702. Preferred connectors are bond wires made of gold or goldalloy. In addition, FIG. 7 depicts the next process step of covering thefirst sheet surface 601 a, the assembled chips 701, and the connectors702 with a polymeric compound 703, preferably an epoxy-based moldingcompound; actually, compound 703 covers the connectors 702 to a height710 over the wire span to ensure complete protection. For many devices,the top surface 703 a of the encapsulation compound is preferablysubstantially planar and parallel to the second sheet surface 601 b.Furthermore, compound 703 is filling the gaps. On the other hand, secondsheet surface 601 b remains uncovered by the encapsulation compound.

FIGS. 8A and 8B illustrate the mechanical grinding step at twocompletion stages, FIG. 8A at an earlier completion stage and FIG. 8B ata later completion stage. For the grinding process (described in moredetail in conjunction with FIG. 9), a rotating grinding wheel 801 isused similar to the wheel conventionally used in the silicon waferback-grinding process. The grinding process attacks the second sheetsurface 601 b (see FIG. 7) and continues to remove metal, until thesheet metal (the “carrier”) is removed, which had remained from theetching step of FIG. 6, and the certain depth 602 a of the gaps etchedin FIG. 6 is reached. At this stage of the grinding step, illustrated inFIG. 8A, the segments 603 and 604 become electrically isolated from eachother.

The grinding step creates a common planar device surface, in which thesegments 603 and 604 and the compound-filled gaps are aligned; in FIG.8A, this common plane is designated 830.

The thickness 560 of the finished device as depicted in FIG. 8Asatisfies the specifications of many products. However, for otherdevices the grinding process may continue, see FIG. 8B, until a thinnerpredetermined thickness 861 of the segments and the overall device isreached.

The device fabrication process may further include the step of attachingreflow metals, such as tin-based solders, to the segments exposed at theplanar device surface 830 to prepare for solder attachment of the deviceto external parts.

FIG. 9 shows schematically components of the back-grinding system usedfor the mechanical grinding process according to the invention. Inprinciple, the system is similar to the ones installed in semiconductormanufacturing for back-grinding silicon wafers. Suitable back-grindingmachines are commercially available, for example, from the companiesDisco, TSK, and Okamoto, all of Japan. A vacuum chuck table 901 has alaminated flat ring 902, which holds a dicing film 903. This film issimilar to the support film commonly used for silicon waferback-grinding and serves to stabilize the molded leadframe-to-be-ground904 against package warpage.

The grinding process is performed by rotating grinding wheel 905 underrunning water and controlled pressure and rotation speeds, withoutgrinding powder. As an example, when wheel type G240-V by the companyDisco is selected, the spindle may rotate at 3000 rpm. The firstgrinding speed of 0.3 μm/s is reached with a first table speed of 300rpm. It is followed by a second grinding speed of 0.2 μm/s.

While this invention has been described in reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. As an example, the invention applies to products using anytype of semiconductor chip, discrete or integrated circuit, and thematerial of the semiconductor chip may comprise silicon, silicongermanium, gallium arsenide, or any other semiconductor or compoundmaterial used in integrated circuit manufacturing.

As another example, the invention applies to many semiconductor devicetypes other than the example of an QFN/SON devices described, forinstance surface mount devices, small outline devices, and leadeddevices.

It is therefore intended that the appended claims encompass any suchmodifications or embodiment.

1. A semiconductor device comprising: a semiconductor chip having anactive and a passive surface, the active surface including contact pads;a plurality of metal segments separated from the chip by gaps, thesegments having first and second surfaces, the second surfaces beingcoplanar with the passive chip surface; conductive connectors spanningfrom the chip contact pads to the first surface of the respectivesegment; and polymeric encapsulation compound covering the active chipsurface, the connectors, and the first segment surfaces, and filling thegaps so that the compound forms surfaces coplanar with the passive chipsurface and the second segment surfaces.
 2. The device according toclaim 1 further comprising reflow metals on the passive chip surface andthe second segment surfaces.
 3. The device according to claim 1 furthercomprising more than one semiconductor chip.
 4. The device according toclaim 1 further comprising at least one passive component.
 5. Asemiconductor device comprising: a plurality of metal segments separatedby gaps, the segments having first and second surfaces, the firstsurfaces suitable for attaching semiconductor chips or conductiveconnectors, the second surfaces being coplanar; a semiconductor chiphaving active and passive surfaces, the active surface including contactpads, the passive surface attached to a metal segment; conductiveconnectors spanning from the chip contact pads to the first surface ofthe respective segment; and polymeric encapsulation compound coveringthe active chip surface, the connectors, and the first segment surfaces,and filling the gaps so that the compound forms surfaces coplanar withthe second segment surfaces.
 6. The device according to claim 5 furthercomprising reflow metals the second segment surfaces.
 7. The deviceaccording to claim 5 further comprising more than one semiconductorchip.
 8. The device according to claim 5 further comprising at least onepassive component.
 9. A method for fabricating semiconductor devicescomprising the steps of: providing a metal sheet having first and secondsurfaces; etching selected portions of the first sheet surface so thatthe etched portions become gaps having a certain depth and selectedlengths and widths between un-etched metal segments, the segmentssuitable for attaching metal connectors; providing semiconductor chipshaving contact pads; attaching each chip in a gap of suitable length andwidth; interconnecting the chip contact pads with respective segmentsusing conductive connectors; covering the first sheet surface includingthe assembled chips and connectors, and filling the remaining gaps, witha polymeric compound; and removing metal of the second sheet surfaceuntil the certain depth of the gaps is reached, thereby electricallyisolating the segments from each other and creating a planar devicesurface.
 10. The method according to claim 9 further comprising the stepof continuing the removing process until a predetermined thickness ofthe segments and the chips is reached.
 11. The method according to claim9 further comprising the step of attaching reflow metals to the chipsand segments exposed at the planar device surface to prepare for solderattachment of the device to external parts.
 12. The method according toclaim 9 wherein the step of removing uses a rotating grinding wheelunder controlled rotation speeds, without grinding powder.
 13. A methodfor fabricating semiconductor devices comprising the steps of: providinga metal sheet having first and second surfaces; etching selectedportions of the first sheet surface so that the etched portions becomegaps having a certain depth and selected lengths and widths betweenun-etched metal segments, the segments suitable for attachingsemiconductor chips or metal connectors; providing semiconductor chipshaving contact pads; attaching each chip on a segment of suitable lengthand width; interconnecting the chip contact pads with respectivesegments using conductive connectors; covering the first sheet surfaceincluding the assembled chips and connectors, and filling the gaps, witha polymeric compound; and removing metal from the second sheet surfaceuntil the certain depth of the gaps is reached, thereby electricallyisolating the segments from each other and creating a planar devicesurface.
 14. The method according to claim 13 further comprising thestep of continuing the removing process until a predetermined thicknessof the segments is reached.
 15. The method according to claim 13 furthercomprising the step of attaching reflow metals to the segments exposedat the planar device surface to prepare for solder attachment of thedevice to external parts.
 16. The method according to claim 13 whereinthe step of removing uses a rotating grinding wheel under controlledrotation speeds, without grinding powder.